Maintenance Registers with Boundary Scan Interface

Concurrent Fault Detector Circuits (CFDCs) are test components of a main system, e.g. an Application Specific Integrated Circuit, and provide the results of the tests in parallel to at least one Error Source Register (ESR). Instead of reading out the ESR in parallel, its contents are copied to a serial shadow register so the contents can be read out in series to an error correcting application, thus reducing the number of output pins and the burden on resources of the main system. The ESR\u27s receipt and transfer of information is under the control of a Boundary Scan Interface. In one embodiment, the test results are prioritized and compared to data in a mask register so that only important errors create a system interrupt which causes the read out of data from the shadow register

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing

The quality of at-speed testing is being severely challenged by the problem that an inter-clock logic block existing between two synchronous clocks is not efficiently tested or totally ignored due to complex test control. This paper addresses the problem with a novel inter-clock at-speed test control scheme, featuring a compact and robust on-chip inter-clock enable generator design. The new scheme can generate inter-clock at-speed test clocks from PLLs, and is feasible for both ATE-based scan testing and logic BIST. Successful applications to industrial circuits have proven its effectiveness in improving the quality of at-speed testing.2006 IEEE International Test Conference, 22-27 October 2006, Santa Clara, CA, US

VirtualScan: a new compressed scan technology for test cost reduction

This work describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction.2004 International Conference on Test, 26-28 October 2004, Charlotte, NC, USA, US

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing

The quality of at-speed testing is being severely challenged by the problem that an inter-clock logic block existing between two synchronous clocks is not efficiently tested or totally ignored due to complex test control. This paper addresses the problem with a novel inter-clock at-speed test control scheme, featuring a compact and robust on-chip inter-clock enable generator design. The new scheme can generate inter-clock at-speed test clocks from PLLs, and is feasible for both ATE-based scan testing and logic BIST. Successful applications to industrial circuits have proven its effectiveness in improving the quality of at-speed testing.2006 IEEE International Test Conference, 22-27 October 2006, Santa Clara, CA, US

VirtualScan: a new compressed scan technology for test cost reduction

This work describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction.2004 International Conference on Test, 26-28 October 2004, Charlotte, NC, USA, US

Turbo1500: Core-Based Design for Test and Diagnosis Using IEEE Std. 1500

Tool support is crucial in widespread adoption of a standard. This article describes a set of tools and associated flow for DFT insertion and test generation based on IEEE Std 1500